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block diagram ordering information the ts3842b and TS3843B series are high performance fixed frequency current mode controllers. this is specifically designed for off-line and dc-to-dc converter applications offering the designer a cost effective solution with minimal external components. this integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power mosfet. also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, programmable output deadtime, and a latch for single pulse metering. this device is available in 8-pin dual-in-line plastic packages as well as the 8-pin plastic surface mount (sop-8). the sop-8 package has separate power and ground pins for the totem pole output stage. the ts3842b has uvlo thresholds of 16v (on) and 10v (off), ideally suited for off-line converters. features general description ts3842b/3843b high performance current mode controller trimmed oscillator discharge current for precise duty cycle control current mode operation to 500khz automatic feed forward compensation latching pwm for cycle-by-cycle current limiting internally trimmed reference with undervoltage lockout high current totem pole output undervoltage lockout with hystersis low start-up and operating current sop-8 dip-8 5.0v reference latching pwm v cc undervoltage lockout oscillator error amplifier 7(12) v c 7(11) output 6(10) power ground 5(8) 3(5) current sense input v ref 8(14) 4(7) 2(3) 1(1) r t /c t voltage feedback input r r + - v ref undervoltage lockout output compensation v cc the document contains information on a new product.specifications and information herein are subject to change without notice. designed for off-line and dc-to-dc converter applications. ts3842/3843bcd dip-8 ts3842/3843bcs sop-8 -20 to +85 device (ambient) package operating temperature
absolute maximum ratings rating symbol value unit total power supply and zener current (i cc +i z ) 30 ma output current source or sink (note 1) io 1.0 a output energy (capacitive load per cycle) w 5.0 j current sense and voltage feedback inputs vin -0.3 to +5.5 v error amp output sink current io 10 ma power dissipation and thermal characteristics plastic dip maximum power dissipation @ t a =25 thermal resistance junction to air plastic sop maximum power dissipation @ t a =25 thermal resistance junction to air p d r ja p d r ja 862 145 1.25 100 mw /w w /w operating junction temperature t j 0 to +150 operating ambient temperature t a -20 to +85 storage temperature range tstg -25 to +150
electrical characteristics characteristic symbol min typ max unit reference output voltage (io=1.0ma,t j = 25 ) vref 4.9 5.0 5.1 v line regulation (v cc =12v to 25v) regline - 2.0 20 mv load regulation (io =1.0ma to 20ma) regload - 3.0 25 mv temperature stability ts - 0.2 - mv/ total output variation over line,load ,and temperature vref 4.82 - 5.18 v output noise voltage (f = 10hz to 10khz, t j =25 ) vn - 50 - v long term stability ( t a =125 for 1000 hours) s-5.0-mv output short circuit current isc -30 -85 180 ma oscillator section frequency t j =25 47 52 57 t a =t low to t high 46 - 60 frequency change with voltage (v cc =12v to 25v) fosc/ v -0.21.0% frequency change with temperature t a =t low to t high oscillator voltage swing ( peak-to-peak) vosc - 1.6 - v discharge current (vosc=2.0v) t j =25 7.5 8.4 9.3 t a =t low to t high 7.2 - 9.5 % khz ma fosc/ t fosc idischg -5.0- reffrence section v cc =15v (note 2), r t =10k, c t =3.3nf, t a =t low to t high (note 3), unless otherwise noted.
electrical characteristics characteristic symbol min typ max unit error amplifier section voltage feedback input (vo=2.5v) v fb 2.42 2.5 2.58 v input bias current (v fb =5.0v) i ib - -0.1 -2.0 a open-loop voltage gain (vo=2.0v to 4.0v) a vol 65 90 - db unity gain bandwidth (t j =25 ) bw 0.7 1.0 - mhz power supply rejection radio (v cc =12v to 25v) psrr 60 70 - db output current sink (vo=1.1v, v fb =2.7v) i sink 2.0 12 - source ( vo=5.0v, v fb =2.3v) i source -0.5 -1.0 - output voltage swing high state (r l =15k to ground, v fb =2.3v) v oh 5.0 6.2 - low state (r l =15k to vref, v fb =2.7v) v ol -0.81.1 current sense section current sense input voltage gain (note 4&5) av 2.85 3.0 3.15 v/v maximum current sense input threshold(note 4) v th 0.9 1.0 1.1 v power supply rejection radio v cc =12v to 25v,note 4 input bias current i ib - -2.0 -10 a propagation delay(current sense input to output) t plh(in/out) -150300ns ma psrr - 70 - db v v cc =15v (note 2), r t =10k, c t =3.3nf, t a =t low to t high (note 3), unless otherwise noted.
electrical characteristics note: 1. maximum package power dissipation limits must be observed. 2. adjust v cc above the start-up threshold before setting to 15v. 3. low duty cycle pulse technique are used during test to maintain junction temperature as close to ambient as possible. t low = -20 ,t high = +85 4. this parameter is measured at the latch trip point with v fb = 0v. v output compensation 5. comparator gain is defined as : av = v current sense input characteristic symbol min typ max unit output section output voltage low state (isink=20ma) v ol -0.10.4 (isink=200ma) - 1.6 2.2 high state (isource=20ma) v oh 13 13.5 - (isource=200ma) 12 13.4 - output voltage with uvlo activated v cc =6.0v,isink=1.0ma output voltage rise time (c l =1.0nf,t j =25 ) tr - 50 150 ns output voltage fall time (c l =1.0nf,t j =25 ) tf - 50 150 ns undervoltage lockout section start-up threshold ts3842b 14.5 16 17.5 TS3843B 7.8 8.4 9.0 minimum operating voltage after turn-on ts3842b 8.5 10 11.5 TS3843B 7.0 7.6 8.2 pwm section duty cycle maximum dcmax 94 96 - minimum dcmin - - 0 total device power supply current start-up, v cc = 14v - 0.25 0.5 operating (note 2) - 12 17 power supply zener voltage (i cc =25ma) vz 30 36 - v v v ol (uvlo) % i cc ma vth v v cc(min) v -0.11.1v v cc =15v (note 2), r t =10k, c t =3.3nf, t a =t low to t high (note 3), unless otherwise noted.
100 90 80 70 60 50 40 800 1.0k 2.0k 3.0k 4.0k 6.0k 8.0k 2.0 0.8 5.0 8.0 20 20 80 10k 20k 50k 100k 200k 500k 1.0m fosc, oscillator frequency (khz) rt. timing resistor (k ? ) r t . timing resistor ( ? ) 1.0 2.0 5.0 100 50 20 10 10k 20k 50k 100k 200k 500k 1.0m fosc, oscillator frequency (khz) % dt. percent output dead-time idischg. discharge current (ma) 75 100 125 50 25 0 -25 -55 t a . ambient temperature ( o c) 9.0 8.0 7.0 8.5 7.5 dmax. maximum output duty cycle (%) 0.15 s/div 2.5v 3.0v 2.0v 20mv/div 10 s/div 200ma/div 2.5v 2.55v 2.45v figure 2 - output dead time vs. oscillator frequency figure 3 - oscillator discharge current vs. temperature figure 4 - maximum output duty cycle vs. timing resistor f igure 5 - error amp small signal transient response figure 6 - error amp large signal transient response figure 1 - timing resistor vs. oscillator frequency
f. frequency (hz) 10 100 1.0k 10k 100k 1.0m 10m 0 30 60 60 80 100 40 20 0 -20 90 120 150 180 excess phase (degrees) avol.open-loop voltage gain (db) iref.reference source current (ma) -24 -20 -16 -12 -8.0 -4.0 0 0 20 40 60 80 100 120 r vref. reference voltage change (mv) r vo.output voltage change (2.0mv/div) 2.0ms/div 2.0ms/div r vo.output voltage change (2.0mv/div) 0 -25 -55 50 25 75 100 125 isc. reference circuit current (ma) 50 70 90 110 t a . ambient temperature ( o c) vo. error output voltage (vo) 0 2.0 4.0 6.0 8.0 vth. current sense input threshold (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 figure 7 - error amp open-loop gain and phase vs. frequency figure 8 - current sense input thresh- old vs. error amp output voltage figure 9 - reference voltage change vs. source current figure 10 - reference short circuit current vs. temperature figure 11 - reference load regulation figure 12 - reference line regulation
io. output load current (ma) 0 200 400 600 800 0 1.0 2.0 3.0 -2.0 -1.0 0 vsat. output saturation voltage (v) 50ns / div 50ns / div 90% 10% vcc. supply voltage (v) vo. output voltage icc. supply current (ma) icc. supply current 010203040 0 5 10 15 20 25 20v / div 100ma / div figure 13 - output saturation voltage vs. load current figure 14 - output waveform figure 15 - output cross conduction figure 16 - supply current vs. supply voltage
figure 17- representative block diagram figure 18 - timing diagram + - reference regulator v cc uvlo + - v ref uvlo 3.6v 36v s r q internal bias + 1.0ma oscillator 2.5v r r r 2r error amplifier voltage feedback input output/ compensation current sense comparator 1.0v v cc 7(12) gnd 5(9) v c 7(11) output 6(10) power ground 5(8) current sense input 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r t c t v ref = sink only positive true logic pin numbers adjacent to terminals are for the 8-pin dual-in-line package. pin numbers in parenthesis are for the d suffix sop-14 package. pwm latch (see text) large r t /small c t small r t /large c t capacitor c t latch "set" input output/ compensation current sense input latch "reset" input output
undervoltage lockout two undervoltage lockout comparators have been incorporated to guarantee that the ic is fully functional before the output stage is enabled. the positive power supply terminal (vcc) and the reference output (vref) are each monitored by separate comparators. each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. the large hysteresis and low start-up current of the ts3842b makes it ideally suited in off-line converter applications where efficient bootstrap start-up technique (figure 33). 36v zener is connected as a shunt regulator from vcc to ground. its purpose is to protect the ic from excessive voltage that can occur during system start-up. the minimum operating voltage for the ts3842b is 11v. output these devices contain a single totem pole output stage that was specifically designed for direct drive of power mosfet?s. it is capable of up to 1.0a peak drive current and has a typical rise and fall time of 50 ns with a 1.0nf load. additional internal circuitry has been added to keep the output in a sinking mode whenever an undervoltage lockout is active. this characteristic eliminates the need for an external pull-down resistor. the sop-8 surface mount package provides separate pins for vc(output supply) and power ground. proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. this becomes particularly useful when reducing the ipk(max) clamp level. the separate vc supply input allows the designer added flexibility in tailling the drive voltage independent of vcc. a zener clamp is typically connected to this input when driving power mosfets in systems where vcc is greater than 20v. figure 25 shows proper power and control ground connections in a current sensing power mosfet application. reference the 5.0v bandgap reference is trimmed to 2.0% on the ts3842b. its primary purpose to supply charging current to the oscillator timing capacitor. the reference has short circuit protection and is capable of providing in excess of 20ma for powering additional control system circuitry. design considerations do not attempt to construct the converter on wire wrap or plug-in prototype boards. high frequency circuit layout techniques are imperative to prevent pulsewidth jitter. this is usually caused by excessive noise pick-up imposed on the current sense or voltage feedback inputs. noise immunity can be improved by lowering circuit impedances at these points. the printed circuit layout should contain a ground plane with low-current signal and high-current switch and output grounds returning separate paths back to the input filter capacitor. ceramic bypass capacitors (0.1 f) connected directly to vcc,vc, and vref may be required depending upon circuit layout.
undervoltage lockout(contd.) this provides a low impedance path for filtering the high frequency noised. all high current loops should be kept as short as possible using heavy copper runs to minimize radiated emi. the error amp compensation circuitry and the converter output voltage divider should be located close to the ic and as far as possible from the power switch and other noise generating components. current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. this instability is independent of the regula- tors closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. figure 19(a) shows the phenomenon graphically. at t 0 , switch conduction begins causing the inductor current to rise at a slope of m 1 . this slope is a function of the input voltage divided by the inductance. at t1, the current sense input reaches the threshold established by the control voltage. this causes the switch to turn off and the current to decay at a slope of m 2 , until the next oscillator cycle. this unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small 1(dashed line). with a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn-on(t 2 ) is increased by 1+ 1m 2 /m 1 . the minimum current at the next cycle (t 3 ) decreases to ( 1+ 1m 2 /m 1 )(m 2 /m 1 ). this perturbation is multiplied by m 2 /m 1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn-on. several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. if m 2 / m 1 is greater than 1, the converter will be unstable. figure 19(b) shows that by adding an artificial ramp that is synchronized with the pwm clock to the control voltage, the 1 perturbation will decrease to zero on succeeding cycles. this compensating ramp (m 3 ) must have a slope equal to or slightly greater than m 2 /2 for stability. with m 2 /2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. the compensating ramp can be derived from the oscillator and added to either the voltage feedback or current sense inputs (figure 32). figure 19 - continuous current waveforms + + control voltage inductor current oscillator period control voltage inductor current oscillator period (a) (b) m 1 m 2 t 0 t 1 t 2 t 3 m 3 m 2 t 4 t 5 t 6 ? ?? ? ?
undervoltage lockout(contd.) figure 20 - external clock synchronization figure 21 - external duty cycle clamp and multi unit synchronization figure 23- soft-start circuit figure 24- adjustable buffered reduc- tion of clamp level with soft-start the diode clamp is required if the sync amplitude is large enough to cause the bottom side of c t to go more than 300mv below ground. virtually lossless current sensing can be achieved with the imple- mentation of a sensefet power switch. for proper operation during over current conditions, a reduction of the ipk(max) clamp level must be implemented. refer to figure 22 and 24. 2(3) ea bias + osc r r r 2r 5(9) 1(1) 4(7) 8(14) r t c t v ref 0.01 external sync input 4 + + + r r r 2r bias osc ea 5(9) 1(1) 2(3) 4(7) 8(14) to additional ts384x's r s q 8 4 6 5 2 1 c 3 7 r a r b 5.0k 5.0k 5.0k f 1.44 (r a r b d max ) r b r a 2r b = = + - 5.0v ref + - s r q bias + osc r r r 2r ea 1.0v 5(9) 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r 1 v clamp r 2 7(12) comp/latch 1.0 ma i pk(max) = = v clamp r s where: 0 v clamp 1.0 v v clamp 1.67 r 2 r 1 1 + 0.33x10 -3 r 1 r 2 r 1 r 2 + + ( ( ) ) v ref ww 5.0v ref + - s r q bias + 1.0ma osc r r r 2r ea 1.0v 5(9) 1(1) 2(3) 4(7) 8(14) c 1.0m 5.0v ref + - s r q bias + 1.0ma osc r r r 2r ea 1.0v 5(9) 1(1) 2(3) 4(7) 8(14) c 1.0m firuge 22-adjustable reduction of clamp level i soft-start =3600c in f + - 5.0v ref + - s r q (11) (10) (8) comp/latch (5) r s 1/4 w v cc v in k m d sensefet g s power ground: to input source return control circuitry ground: to pin (9) v pin 5 r s i pk x r ds(on) r dm(on) r s if: sensefet = mtp10n10m r s = 200 then : v pin 5 0.075 i pk (12) = = + rs figure 25- current sensing power mosfet
undervoltage lockout(contd.) figure 30- latched shutdown bias + osc r r r 2r ea 5(9) 1(1) 2(3) 4(7) 8(14) mcr 101 2n 3905 2n 3903 1.0 ma the mcr101 scr must selected for a holding of less than 0.5ma at t a (min.). the simple two transistor circuit can be used in place of the scr as shown. all resistors are 10k. + - 5.0v ref + - s r q 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in c r 7(12) comp/latch the addition of rc filter will eliminate instability caused by the leading edge spike on the current waveform. figure 26- current waveform spike suppression figure 27- mosfet parasitic oscillations s r 5.0v ref q 7(1 1) 6(10) 5(8) 3(5) r s q1 v cc v in 7(12) r g comp/latch + - + - figure 28- bipolar transistor drive 6(10) 5(8) 3(5) r s q1 v in c1 base charge removal i b + - 0 figure 29- isolated mosfet drive s r 5.0v ref q 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in isolation boundary v gs waveforms + - 0 + - 0 50% dc 25% dc i p k v (p in1) 1.4 3 r s n s n p comp/latch 7(12) r c n s n p + - + - = _ ( ) the totem-pole output can finish negative base current for en- hanced transistor turn-off with the additions of capacitor c1.
undervoltage lockout(contd.) figure 32-slope compenstaion + - + - 5.0v ref 36v s r q bias + 1.0ma osc r r r 2r ea 1.0v 7(12) 7(11) 6(10) 5(8) 3(5) r s v cc v in 1(1) 2(3) 4(7) 8(14) r t c t m -3.0m -m r f c f r i r d from v o r slope mps3904 5(9) comp/latch q1 the buffered oscillator ramp can resistively summed with either the voltage feedback or current sense inputs to provide slope c ompensation. figure 31-error amplifier compensation + r 2r 1.0ma ea 2(3) 5(9) 2.5v 1(1) r f c f r d r i from v o error amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. + r 2r 1.0ma ea 2(3) 5(9) 2.5v 1(1) r f c f r d r p from v o c p r i
undervoltage lockout(contd.) figure 33-27 watt off-line regulation all outputs are at nominal load currents unless otherwise noted. mur1 10 + - + - s r + r r 5.0v ref q bias ea 5(9) 7(11) 6(10) 5(8) 3(5) 0.5 mtp 4n50 1(1) 2(3) 4(7) 8(14) 10k 4700pf 470pf 150k 100 pf 18k 4.7k 0.01 100 + 1.0k 115 vac 4.7 w mdr 202 250 56k 4.7k 3300 pf 1n4935 1n4935 ++ 68 47 1n4937 1n4937 680pf 2.7k l3 l2 l1 ++ ++ ++ 1000 1000 2200 10 10 1000 5.0v/4.0a 5.0v rtn 12v/0.3a -12v/0.3a mur1 10 mbr1635 t1 22 osc 7(12) comp/latch vref 1.0ma 2r r 1.0v + + 12v rtn - test conditions results line regulation: 5.0v =50mv or 0.5% 12v =24mv or 0.1% load regulation: 5.0v vin=115vac, iout =1.0a to 4.0a =300mv or 3.0% 12v vin=115vac,iout=100ma to 300ma =60mv or 0.25% output ripple: 5.0v 40mvp-p 12v 80 vp-p efficiency vin=115vac 70% vin=95 to 130 vac vin=115vac t1 primary : 45 turns #26 awg secondary 12v : 9 turns #30 awg (2 strands ) bifiliar wound. secondary 5.0v : 4 turns (six strands) #26 hexfiliar wound. secondary feedback : 10 turns #30 awg (2 strands) bifiliar wound. core : ferroxcube ec35-3c8 bobbin : ferroxcube ec35pcb1 gap : ? @0.10? for a primary induc- tance of 1.0mh. l1: 15 h at 5.0a, coilcraft 27156. l2,l3: 25 h at 1.0a, coilcraft 27157.
undervoltage lockout(contd.) figure 34-33 watt off-line flyback converter with soft-start and primary power limiting t1 coilcraft 11-464-16, 0.025? gap in each leg bobbin : coilcraft 37-573 windings: primary, 2 each: 75 turns #26 awg bifilar wound feedback: 15 turns #26 awg secondary , 5.0v: 6 turns #22 awg bifilar wound secondary , 5.0v: 14 turns #24 awg bifilar wound l1 coilcraft z7156. 15 f @ 5.0a l2,l3 coilcraft z7157. 25 f @ 1.0a optional r.f.i filter 15 cold t 1.0a 3 each 0.0047 ul / csa 1n4003 1n4001 1n4742 1n4687 1n4148 1n4934 1n4934 1n5824 3/200 vac 180/ 200v 7.5k 25k 2.2m 0.01 33k 22k pout pout 5.0k 0.01 1 2 3 14 13 12 10 6.8k 27k 2.7k 1.5k 8.2k 11k 8 9 7 6 5 4 10 0.001 47k e c vcc comp pj34060 vref c t r t d t gnd 200 47 mps mps a05 a55 10/25v 1.0 l1 l2 l3 100 /10v 2200 /10v 1000 /25v 1000 /25v 10 /35v 10 /35v common 5.0v /3.0a 12v /0.75a 12v /0.75a 1n4934 47 / 25v mje 13005 test conditions results line regulation 5.0v vin=95 to 135 vac, io=3.0a 20mv 0.40% line regulation 12v vin=95 to 135 vac, io=0.75a 52mv 0.26% line regulation 5.0v vin=115 vac, io=1.0 to 4.0a 476mv 9.5% line regulation 12v vin=115 vac, io=0.4 to 0.9a 300mv 2.5% line regulation 5.0v vin=115 vac, io=3.0a 45 mvp-p p.a.r.d. line regulation 12v vin=115 vac, io=0.75a 75 mv p-p p.a.r.d. vin=115 vac, io(5.0v)=3.0a io(12v)=0.75a efficiency 74%
pin function description pin no. function description 1 compensation this pin is the error amplifier output and is made available for loop compensation 2 voltage feedback this is the inverting input of the error amplifier. it is normally connected to the switching power supply output through a resistor divider. 3 current sense a voltage proportional to inductor current is connected to this input. the pwm uses this information to terminate the output switch conduction. 4 r t /c t the oscillator frequency and maximum output duty are programmed by connecting resistor r t to vref and capacitor c t to ground operation to 500khz is possible 5gnd this pin is the combined control circuitry and power ground (8-pin package only). 6output this output directly drives the gate of a power mosfet. peak current up to 1.0a are sourced and sunk by this pin. 7 vcc this pin is the positive supply of the control ic. 8vref this pin is the reference output. it provides charging current for capacitor c t through resistor r t . 5 8 4 1 1 4 5 8 dip-8 sop-8 pin : 1. compensation 2. voltage feedback 3. current sense 4. r t / c t 5. gnd 6. output 7. v cc 8. v ref
operating description the ts3842b series are high performance, fixed frequency, current mode controllers. they are specifically designed for off-line and dc-to-dc converter applications offering the designer a cost effective solution with minimal external components. a representative block diagram is shown in figure 17. oscillator the oscillator frequency is programmed by the values selected for the timing components r t and c t . capacitor c t is charged from the 5.0v reference through resistor r t to approximately 2.8v and discharge to 1.2v by an internal current sink. during the discharge of c t , the oscillator generates an internal blanking pulse that holds the center input of the nor gate high. this causes the output to be in a low state, thus producing a controlled amount of output deadtime. figure 1 shows r t versus oscillator frequency and figure 2, output deadtime versus oscillator frequency, both for given values of c t . note that many values of r t and c t will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. the oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within 10% at t j =25 . these internal circuit refines minimum variations of oscillator frequency and maximum output duty cycle. the results are shown in figure 3 and 4. in many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. this can be accomplished by applying a clock signal to the circuit shown in figure 20 for reliable locking. the free-running oscillator frequency should be set about 10% less than the clock frequency. a method for multi unit synchronization is shown in figure 21. by tailling the clock waveform, accurate output duty cycle clamping can be achieved. error amplifier a fully compensated error amplifier with access to the inverting input and output is provided. it features a typical dc voltage gain of 90db, and a unity gain bandwidth of 1.0mhz with 57 degrees of phase margin (figure 7). the non-inverting input is internally biased at 2.5v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input. the maximum input bias current is -2.0 a which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. the error amp output (pin 1) is provided for external loop compensation (figure 31). the output voltage is offset by two diode drops ( 1.4v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that no drive pulses appear at the output (pin 6) when pin 1 is at its lowest state (v ol ). this occurs when the power supply is operating and
current sense comparator and pwm latch the ts3842b operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level estab- lished by the error amplifier output/compensation (pin 1). thus the error signal controls the peak inductor current on a cycle-by-cycle basis. the current sense comparator pwm latch configu- ration used ensures that only a single appears at the output during any given oscillator cycle. the inductor current is converted to a voltage by inserting the ground referenced sense resistor r s in series with the source of output switch q1. this voltage is monitored by the current sense input (pin 3) and compared to a level derived from the error amp output. the peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: i pk = [v(pin 1) - 1.4v] / 3r s abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. under these conditions, the current sense comparator threshold will be internally clamped to 1.0v. therefore the maximum peak switch current is: i pk (max) = 1.0v / r s when designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of r s to a reasonable level. a simple method to adjust this voltage is shown in figure 22. the two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. erratic operation due to noise pickup can result if there is an excessive reduction of the i pk (max) clamp voltage. a narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. this spike is due to the power transformer interwinding capacitance and output rectifier recovery time. the addition of an rc filter on the current sense input with a time constant that approximates the spike duration will usually eliminate the instability: refer to figure 26. r f(min) = [3x(1.0v)+1.4v] / 0.5ma = 8800 ? the load is removed, or at the beginning of a soft-start interval (figure 23,24). the error amp minimum feedback resistance is limited by the amplifier?s source current (0.5ma) and the re- quired output voltage (v oh ) to reach the comparator?s 1.0v clamp level:
sop-8 1 4 5 8 r j f x 45 a b p d k c g m o dip-8 14 5 8 a b j g d k l m c min max min max a 4.80 5.00 0.189 0.196 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g k 0.10 0.25 0.004 0.009 m 0707 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 1.27bsc 0.05bsc symbols millimeters inches min max min max a 9.07 9.32 0.357 0.367 b 6.22 6.48 0.245 0.255 c 3.18 4.43 0.125 0.135 d 0.35 0.55 0.019 0.020 g j 0.29 0.31 0.011 0.012 k 3.25 3.35 0.128 0.132 l 7.75 8.00 0.305 0.315 m-10 -10 2.54bsc 0.10bsc symbols millimeters inches

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